Memory is typically a cyclical industry that is lower margin and lumpy, yet it is seeing a newfound resurgence from AI that is strong enough to transform commoditized hardware into a secular trend as the AI economy is built out. AI servers use more DRAM and NAND than traditional servers, relying heavily on high-bandwidth memory (HBM) for training and inference.
We first touched upon the rising importance of the memory market in AI GPUs in the summer of 2023 within our AMD and Lam Research analyses, and provided a closer look in November 2023 in the analysis, 2024 Trend: Memory and PC Rebound. We also dove further into HBM’s growth opportunities in December 2023 with our Micron deep dive, Micron: AI Offers a Multifaceted Secular Growth Tailwind.
As is stands, the AI-driven demand for memory (especially HBM and high-performance DRAM) is still in the early stages of a multiyear growth cycle. The company’s CEO and Chairman, Sanjay Mehrotra, also mentioned in the September earnings call, “Memory is very much at the heart of this AI revolution. This means a tremendous opportunity for memory and certainly a tremendous opportunity for HBM."
The HBM market is projected to reach $35 billion this year, doubling YoY, with Micron’s September results confirming that the market was well on track to be over $30 billion as of Q3. Looking ahead, the shift to HBM4 with Nvidia’s Rubin architecture and AMD’s MI400 series will represent another important growth lever come 2026 as HBM content per GPU and per rack surges, paving the way for HBM to potentially triple again by as early as 2028.
Not only is HBM a focal point due to its rising importance and thus increasing content per GPU, but other memory products are quickly coming to the forefront, notably low-power DDR5 memory (LPDDR5X) and data center solid state drives (SSDs).
Below, we look at the memory products front and center of this AI-driven cycle, structural drivers behind rising AI memory demand such as AI inference, supply and inventory constraints driving prices rapidly higher, long-term growth outlooks and more.
Overview: DRAM and NAND’s Role in AI
Demand for high-capacity memory is driven by generative AI and LLMs, which both require significant amounts of computing power and substantial amounts of DRAM to meet elevated performance requirements. Within DRAM, demand is focused more specifically around high-bandwidth memory (HBM) and double-data rate 5 DRAM (DDR5) for its increasing content in AI accelerators — SK Hynix’s head of DRAM marketing Park Myung-soo has explained in the past that “an AI server requires 500-gigabyte (GB) or larger high bandwidth memory (HBM) chips and at least 2-terabyte (TB) DDR5 chips.” Now, we’re seeing nearly that amount of HBM being put on a single GPU rather than an 8-GPU system.
High bandwidth memory (HBM) offers higher bandwidth, capacity, performance, and lower power by vertically stacking up to twelve DRAM memory chips to shorten how far data has to travel, while also allowing for smaller form factors. Stacked memory chips are connected through something called “through silicon vias” or TSVs.
HBM is now mission-critical, especially for inference, as increasing bandwidth and capacity per HBM generation paves the way for significant leaps in throughput with each GPU generation. Currently, the leading AI accelerators from Nvidia and AMD utilize HBM3e, an enhanced HBM3, while the next-gen Rubin and MI400 architectures are set to bring HBM4 mainstream next year – more on this below.
DDR5 DRAM, or double data rate 5, is aimed to double bandwidth and data transfer speeds at a lower latency and power consumption than its predecessor, DDR4. DDR5 memory chips can be mounted on circuit boards to create memory modules, for use in servers or PCs. DDR5’s increased bandwidth allows for faster processing for memory-intensive applications, such as generative AI and training LLMs. Memory giant SK Hynix saw high-capacity DDR5 (>128GB) revenue more than double QoQ in Q3.
Demand for a low-power DDR5 variant, LPDDR5X, is rising sharply due to its role in Nvidia’s Grace and Vera CPUs, as LPDDR5x is delivering up to 5X better throughput, a more than 35% increase in memory bandwidth with up to 77% lower power consumption. This combination can improve system power efficiency (performance per watt) by up to 10%, per Micron.
Emerging with Nvidia’s GB300 racks (and soon Rubin racks) are SOCAMM modules, which combine LPDDR5X with a Compression Attached Memory Module (CAMM). SOCAMM modules can deliver up to 2.5X higher bandwidth with lower power consumption and a smaller footprint versus traditional RDIMMs (registered dual in-line memory modules).
Not to be forgotten is memory’s second half, NAND, as it also plays a vital yet less visible role in AI, as its high-capacity, reliable storage is increasingly important in meeting growing inference demands. NAND’s importance is primarily concentrated to NAND-flash based data center solid-state drives (SSD).
SSDs can boast superior performance in speed, latency, energy efficiency and reliability compared to hard disk drives (HDD). The high-speed read capabilities of SSDs help process vast datasets in training large LLMs and multi-modal models, as well as store model checkpoints. For inference, SSDs are typically used to store ‘hot’ data, or data needing to be accessed frequently, making them crucial for inference workloads.
HBM3e, HBM4 and the Need for Increased Memory Bandwidth
HBM3e is the primary version of HBM shipping currently, supporting both Nvidia’s H200 and Blackwell architectures, as well as AMD’s Instinct MI350 series and Google’s TPU v7 Ironwood. HBM4, the next generation, is expected to support Nvidia’s upcoming Rubin platform later in 2026, along with AMD’s Instinct MI400 series.
The reason that AI accelerators are quickly upgrading to the next generation of HBM is because HBM capacity and bandwidth are consistently increasing, which, when combined with increasing capacity per chip, translates directly to massive leaps in throughput, or tokens processed per second. This means that newer chip generations, such as the shift from Nvidia’s Hopper generation to Blackwell, are exponentially more performant on LLM inference workloads.
For example, HBM2e, used on Nvidia’s H100, delivered a modest 3.6 Gb/s data rate (speed of data transfer), leading to 461 GB/s of bandwidth per HBM cube. With HBM3, data rates improved to 6.4 Gb/s and stack heights moved from 12 to 16, thus boosting bandwidth by more than 75% to 819 GB/s.
Source: Rambus
With HBM3e, data rates increased substantially to 9.6 Gb/s, boosting bandwidth to 1.23TB/s, or nearly 3X that of HBM2e. Translating this to Nvidia’s H200 meant that it could deliver 1.4X to 2X faster LLM inference versus the H100 as bandwidth per chip rose from 3TB/s to 4.8TB/s and HBM capacity rose 1.76X from 80GB to 141GB.
Source: Nvidia
With HBM4, the main upgrade is a doubling of interface bits from 1,024 to 2,048, or the number of data bits that can be transferred simultaneously between the memory chip and the GPU. This means that even at the JEDEC standard of 8 Gb/s data rate, a modest decline from HBM3e, bandwidth per HBM4 stack rises to more than 2 TB/s, a 2.5X boost from HBM3 and a ~66% increase from HBM3e. However, Micron claims that its HBM4 boosts data rate to 11 Gb/s, delivering 40% higher bandwidth at 2.8 TB/s per stack, along with 20% better power efficiency and 60% better performance versus HBM3e.
While these increases may not seem significant when looking simply at upgrades per HBM generation, looking at the exponential increases in bandwidth and inference performance per GPU generation shows a better picture.
Nvidia’s 8-GPU HGX H100 system delivered a mere 24 TB/s of aggregate memory bandwidth, yet the HGX B200 system boosted that ~2.6X to 62 TB/s with the shift to HBM3e and more HBM3e content (more on this below).
The scale-up architecture of Nvidia’s GB200 and GB300 NVL72 brought a massive boost to aggregate memory, with both rack-scale solutions offering 576 TB/s, or 24X more than the HGX H100 systems. Nvidia says the GB200 can offer throughput of up to 116 tokens/s on GPT-MoE-1.8T model, a 30X improvement on real-time LLM inference versus the HGX H100, with performance gains also aided by improvements in NVLink and CX8 network interface cards.
Source: Nvidia
Nvidia’s upcoming Vera Rubin architecture will boost aggregate memory bandwidth by as much as 8X from here over the next two years.
Nvidia’s upcoming Vera Rubin NVL144 is expected to take aggregate memory bandwidth to 1.4 PB/s, and 1.7 PB/s with the CPX platform. This is the equivalent of 1,400 TB/s to 1,700 TB/s, or a ~2.4X to ~3X increase versus the GB200/GB300 racks. Jensen Huang claims that the NVL144 system bandwidth is “the entire data usage of the Internet in one second.”
With the NVL576, aggregate memory bandwidth will continue to surge, with the rack boasting 4.6 PB/s, or 4,600 TB/s of bandwidth. This is another roughly 3X boost to the NVL144, and compared to the GB200/GB300, a massive 8X increase in just two years.
HBM’s Longer-Term Tailwind: Capacity per Chip Surging
HBM capacity per chip continues to rise with each new generation of GPU, and this is a primary contributing factor behind the surging aggregate memory bandwidth discussed above, paving the way for accelerated throughput gains and inference performance. For example, we’ve seen a ~3.5x increase in HBM content in short fashion on Nvidia’s GPUs within about three years’ time frame:
- The H100 featured 80GB of HBM2e content per chip. This chip began shipping in Q4 2022 and ramped in early 2023.
- The H200 featured 141GB of HBM3e content per chip, 1.76x higher than its predecessor.
- The B200 features 180GB of HBM3e content, more than double the H100 and a 28% increase versus the H200. In an 8-GPU server configuration, the B200 boasted 1.44TB of HBM content.
- The B300 boasts 288GB of HBM3e content, a 60% increase versus the B200 and over 3.5x more than the H100. In an 8-server configuration, the B300 has 2.3TB of HBM content. This chip is beginning to ship now in Q3-Q4 2025.
- The upcoming Rubin chip will remain at 288GB, but transition to HBM4 for more bandwidth.
Putting in context Nvidia’s rack-scale solutions, the GB200 and GB300 NVL72, shows just how rapidly HBM content is increasing. The GB200 supports up to 13.4TB of HBM content, while the GB300 supports up to 21.7TB of HBM, nearly 34X higher than the 640GB of HBM content in the 8-GPU DGX H100 servers.
AMD is also showing surging memory requirements, to the tune of 3.5X across two main generations:
- The Instinct MI250 featured 128GB of HBM2e memory.
- The MI350X featured 288GB of HBM3e memory, a 125% increase versus the MI250 and on par with Nvidia’s Blackwell Ultra.
- The MI400 series is expected to feature 432GB of HBM4 memory, a 50% increase versus the MI350X and the Blackwell Ultra. In the Helios rack configuration slated for 2026, the MI400 will boast 31.1TB of HBM content, 1.5x more than the GB300 NVL72.
Packing more HBM per chip is also not exclusive to GPUs, with Google’s TPUs notably seeing a 6X jump in HBM capacity over one generation (one year) and a 12X increase in two generations:
- Google’s TPU v5e, released to general availability in 2023, featured 16GB of HBM capacity.
- TPU v6e (Trillium), released in 2024, doubled HBM capacity per chip to 32GB.
- TPU v7 (Ironwood), released this year, boosted HBM capacity by 6X over Trillium to 192GB per chip, or 12X growth from v5e.
This surge is expected to continue through 2027 as HBM4 and then HBM4e come online – it has been estimated that in a 20-high configuration could pack 80GB of memory per HBM chip, up from 36GB per 12-high HBM3e cube today. Assuming similar usage of eight cubes, this could take memory per GPU up from 288GB in Nvidia’s B300 to 640GB in future chips.
HBM Market Doubling in 2025, Expected to Triple Again by as Early as 2028
The HBM market is forecast to double this year to approximately $35 billion, up from less than $18 billion in 2024, with growth driven by increasing content per GPU such as that with Blackwell and Blackwell Ultra as well as from capacity constraints. As of Q3, HBM is now likely above a $30 billion annualized run rate, supported by comments from Micron last quarter that its HBM revenue grew to almost $2 billion; with HBM share expected to nearly match its DRAM share (of 22% in Q2 to 25.7% in calendar Q3), this would imply the HBM market is likely in the mid-$8 billion range, or around $32-33 billion annualized. HBM’s share of DRAM revenue is also rising sharply, expected to rise ten points this year, from 18% in 2024 to 28% in 2025, with more growth ahead through 2030.
Through 2026 and 2027, the outlook for HBM remains fairly positive, with SK , SK Hynix, Samsung and Micron already selling out of HBM3e and HBM4 capacity through the end of 2026. This underscores the robust demand environment stemming from AI accelerators, with Micron seeing HBM bit shipments outpacing DRAM bit growth, but also may limit revenue upside as prices have been contracted over the next four quarters.
On pricing, HBM4 is expected to carry a significant premium to HBM3e, currently used for Nvidia’s Grace Blackwell chips. Analysts from UBS had estimated that HBM4’s price premium could be as much as 30%, though reports of Samsung’s discussions over HBM4 supply with Nvidia dwarfed that – Samsung was said to be targeting price parity with SK Hynix on HBM4 around $500, up ~50% from the mid-$300s for HBM3e. These price increases will support strong growth as HBM4 volumes ramp.
Looking forward, industry analysts project the HBM market to reach $98 billion to $100 billion by 2030, representing a 31.5% CAGR from 2024’s $18 billion, outpacing DRAM’s growth by 3X, which is expected to rise at an 11.7% CAGR to $194 billion. As a result, HBM’s share of DRAM revenue is expected to surpass 50%.
However, in its Q1 report, Micron said it now expects the HBM TAM to reach $100 billion as early as 2028, two years sooner than its prior forecast. This would represent a ~42% CAGR from $35 billion, or more than 10 points faster than the base case forecasts.
HBM’s Challenges: No Tail-End to Shipments, Supplier Shifts
The reason that HBM can be such a challenging market is two-fold – supplier qualifications can (and do) change rather quickly between generations for SK Hynix, Samsung and Micron, and the winner is oftentimes determined by time-to-market, or whichever company can hit mass production first.
Micron executives explained that HBM is unlike standard memory products, and that they do not expect a long tail in these products, meaning that once the next generation comes online and ramps (HBM3 to HBM3e, HBM3e to HBM4, etc), demand for the old generation dissipates quickly. This in turn means that whichever suppliers can either qualify first and reach mass production first have an advantage when it comes to revenue and even margins. For example, SK Hynix was the main supplier of HBM for Nvidia’s H100, yet Micron was the main supplier for the H200.
For HBM4, SK Hynix said in early September that it had finished development of HBM4 and was ready for mass production, while Micron also announced that month that it had begun shipping HBM4 samples to customers. On the other hand, Samsung just finished development of HBM4 in early December and began shipping samples to Nvidia. However, SK Hynix is reportedly delaying the start of mass production from Q2 2026 to Q3 2026 to better align with Rubin’s ramp.
Rising Demand for LPDDR5X and the DDR5 Profitability Dilemma
Demand for LPDDR5X is rising sharply due to its role in Nvidia’s Grace and Vera CPUs, as LPDDR5x is delivering up to 5X better throughput, a more than 35% increase in memory bandwidth with up to 77% lower power consumption versus typical DDR5.
Low power is critical with Nvidia’s GB racks as well as Rubin, as power consumption has been surging per rack, and already pushing the upper boundaries of what current data center infrastructure can handle. Current builds, such as Vantage’s upcoming 1.4 GW campus in Texas for Oracle, are only designed for ultra-high density racks up to 250kW, meaning these new facilities could quickly be phased out and require new infrastructure to accommodate increasingly power hungry racks.
Nvidia’s GB300 and Rubin platforms will use a purpose-built SOCAMM module optimized for AI servers, which combines LPDDR5X with a Compression Attached Memory Module (CAMM), aimed at maximizing performance and reducing power consumption. This is currently provided by Micron, which reported 50% QoQ in LPDDR revenue to a new record last quarter.
When comparing to smartphones, the usual destination for LPDDR memory, the content demands for AI servers are profoundly large:
“Indeed, each Grace CPU in today's platform is equipped with 480 GB of LPDDR5X memory (a premium smartphone uses 16 GB of LPDDR5X), but this is going to at least double with Vera CPUs, possibly straining LPDDR5X supply.”
So not only do you have Nvidia’s Blackwell and Blackwell Ultra lines ramping, with those consuming 30X LPDDR5X memory as a typical smartphone, but that gap is poised to widen tremendously later next year as Rubin ramps, with the Vera CPU expected to contain 1.5TB of LPDDR5X, more than 3X the Grace CPU and as much as almost 94 smartphones.
Keep in mind that the 480GB for the Grace CPU and the 1.5TB for Vera CPU are per chip, per chip, meaning that the GB200 NVL72 rack featuring 36 CPUs will consume 17.28TB per rack. per rack. For the Rubin NVL144, with the same 36 CPU count, LPDDR5X content would surge to 54TB per rack, and in the NVL576, with 144 CPUs, content quadruples to 218TB per rack218TB per rack. That is the equivalent of 13,625 premium smartphones.
Nvidia’s demand needs are expected to place substantial upward pressure on prices, as Counterpoint Research believes it now is an LPDDR “customer on the scale of a major smartphone maker — a seismic shift for the supply chain which can’t easily absorb this scale of demand.”
Global DRAM Market Surges 31% QoQ in Q3, Q4 Pricing to Remain Strong
You would be hard pressed to find another segment of the AI data center industry posting growth to this degree on a sequential basis. Data from TrendForce estimates that the global DRAM market recorded growth of 30.9% QoQ in calendar Q3 to $41.4 billion. In dollar terms, this represented QoQ growth of ~$9.7 billion, or nearly as large of a QoQ jump as Nvidia reported in its most recent quarter. This growth was driven by “significant increases in conventional DRAM contract prices, higher bit shipments, and growing HBM volumes.”
For a supplier breakdown, SK Hynix’s revenue grew 12.4% QoQ to $13.75 billion, fueled by seasonal price increases and significant bit shipment growth. Samsung also reported similar significant growth in bit shipments, with revenue up 30.4% QoQ to $13.50 billion. Micron followed with a substantial 53.2% QoQ increase to $10.65 billion, per TrendForce (note that this is for calendar Q3 which does not align with Micron’s fiscal year calendar).
As of November, TrendForce estimates that DRAM contract prices will accelerate into Q4, predicting conventional DRAM contract prices will surge by another 45% to 50% QoQ, while total contract prices (which includes HBM) will increase by 50% to 55% QoQ – this is a substantial uplift from projections for 18-23% QoQ growth in Q4 at the end of October.
Contributing to strong pricing is DDR5 DRAM, where prices rapidly skyrocketed – from late September to early November, prices have as much as quadrupled, with impacts felt most on consumer products. Samsung also reportedly just boosted DDR5 prices by 100%, citing no stock left.
However, revenue growth in Q4 will likely be lower than pricing as bit shipments are projected to decline sequentially due to rapid inventory depletion. DRAM supplier inventory levels are projected to range between two to four weeks, a major crunch from 5.5 weeks on average last quarter and more than 15 weeks at the start of the year.
Turning to 2025 as a whole, HBM is expected to be a primary growth contributor for the DRAM industry. Current projections have DRAM revenue rising ~35% YoY, or $32 billion, to $127 billion in 2025, meaning HBM is contributing more than half of that dollar growth at ~$17 billion. This is also marking a rapid recovery from 2023’s trough of $52 billion, with the $127 billion projection representing two-year growth of 148%.
For 2026, it is these tailwinds above, along with tight supply, that can continue to drive strong growth in the DRAM market moving through the year, especially as HBM4 begins to ramp initially with Nvidia’s Rubin platform along with AMD’s MI400 platform.
Inference is Creating a Secular Tailwind for Data Center NVMe SSDs
Data center solid state drives (SSDs), such as those based on NAND flash memory, are an often overlooked but equally important memory component when it comes to AI training and inference. This is because data center SSDs offer higher read-write speeds critical for accessing and transferring data rapidly, along with higher performance and energy efficiency, making them vital for larger-scale AI training and inference workloads.
NVMe (Non-Volatile Memory Express) is a protocol designed specifically for NAND-flash based SSDs that optimizes performance by reducing latency and increasing data transfer speeds by utilizing the PCIe bus. This helps provide the high throughput and fast data transfer speeds necessary for AI workloads – NVMe SSDs can increase performance by more than 2X versus SATA SSDs.
There are five main types of NAND flash used in SSDs, delineated by the number of bits of data that can be stored per cell:
- SLC (single-level cell): Stores one bit of data per cell, meaning data can be retrieved faster. SLC offers the best performance and highest endurance, though it is typically the most expensive.
- MLC (multi-level cell): Stores two bits of data per cell, allowing for a higher data density or higher capacity, though this comes at the expense of performance and endurance. MLC is typically found in consumer NAND products.
- TLC (triple-level cell): Stores three bits per cell, increasing density and capacity and reducing cost, but also increasing chance for error.
- QLC (quad-level cell): Stores four bits per cell, providing significant storage capacity (4X that of SLC) and lower costs, making QLC suitable for large-capacity solid-state drives. Meta has made the case for QLC SSDs in data center applications due to the higher density and improved power efficiency versus TLCs at a price that allows for significant scaling, though it says price is not yet competitive enough for broader deployments.
- PLC (penta-level cell): The next evolution of NAND flash that stores five bits per cell, aiming for significant high density storage but also facing high error rates.
AI training and inference are two main long-term drivers for SSD demand, which is projected to rise ~6X from 2024 to 2030, from 181 exabytes (EB, or equal to 181,000,000 TB) to 1,078 EB, under McKinsey’s base case scenario. Training demand projected to rise at a 62% CAGR to from 7 EB in 2024 to 127 EB by 2030. On the flipside, demand from AI inference is expected to grow at a 105% CAGR from 6 EB to 447 EB by 2030, giving inference a 41% share of demand versus less than 12% for training.
This is not only driven by development of more LLMs, but also the increasing size and complexity of frontier models, where training data sets and context windows for inference are getting increasingly large.
For example, EpochAI estimates that training data set sizes are rising 3.7X per year on average, or nearly doubling every six months. There are some models that are scaling much quicker. For example, Meta’s Llama2-70B from 2023 was trained on 2 trillion tokens, while Llama3-70B, from 2024, was trained on 15 trillion tokens, a 7.5X increase. Multi-modal models, those integrating audio, video, image or more, are also likely to require significantly more SSD storage, with McKinsey estimating in the hundreds of TBs depending on the mix of data needing to be stored.
Source: EpochAI
Looking at tensor parallelism from a memory perspective also shows why the ability to distribute workloads across tens to thousands of GPUs is such a game-changer for AI training and inference. After accounting for memory required to store model parameters and for the activation buffer, a single AMD MI300X GPU can handle a max request of ~6,500 tokens on Llama-70B, per TensorWave. However, when you distribute model parameters across 8 GPUs along with the same buffer, that 8-GPU server could now handle a max request of 523,000 tokens, an ~80X increase, with gains that only compound as server size and memory increase.
The increasing size and complexity of models also ties directly to a major pain point when it comes to inference: “As models grow in complexity and require longer contexts, their memory footprint expands beyond what a single GPU can handle. This results in inefficiencies where GPUs are memory-starved, causing significant bottlenecks in AI token generation.”
To put this GPU memory bottleneck in real-life application for inference, AI inference acceleration startup WEKA states that when it tested Llama-3.1 70B with no optimizations, a 100K token prompt took 24 seconds to pre-fill into the model before any output could be generated, but “extending GPU memory to ultra-fast storage [NVMe SSDs] can dramatically improve token processing efficiency.” When configuring an Nvidia DGX H100 server with an 8-node exabyte-scale NVMe SSD pod, WEKA says its “tests demonstrated a staggering 41x reduction in prefill time on LLaMA3.1-70B, dropping from 23.97 seconds to just 0.58 seconds,” significantly improving model efficiency with zero optimizations – simply from adding SSDs to extend GPU memory. This pre-fill time would feel near instantaneous for an end user versus a 24 second delay.
Other long-term growth vectors include increased adoption of retrieval augmented generation (RAG), which “assembles companies’ own data into vectorized databases, which models then refer to, improving the accuracy and specificity of outputs.” RAG would then require two forms of storage – active storage of useful data, and vector database storage to organize that active data to be accessible by LLMs.
Source: McKinsey
A more rapid uptake of RAG or faster multi-modal model adoption could push data center SSD demand up to a 42% CAGR through 2030, reaching 1,490 EB or ~8X 2024’s demand, while slower uptake could see demand rise at a 25% CAGR to 702 EB, or ~4X 2024’s demand.
Data Center SSD Revenue Up 28% QoQ in Q3
Similar to DRAM, data center SSD shipments and prices were strong in Q3, driven by hyperscaler demand for AI infrastructure and general-purpose servers. Revenue from the top five companies – Samsung, SK, Micron, Kioxia and SanDisk – rose ~28% QoQ to a new record at $6.54 billion, per TrendForce. Notably, this was broad-based strength, with growth at the five firms all ranging between 26-30% QoQ.
For Q4, there are a few dynamics in play that are likely to keep prices and thus revenue growth strong. For example, supplier inventories are expected to have fallen sharply, from 10-15 weeks in early Q3 to just 7-10 weeks at the start of Q4, which was said to be ‘below healthy levels’, with enterprise SSD supply growth substantially lagging demand. SanDisk says that its storage-focused SSD is “growing in demand with 2 hyperscaler qualifications underway and a third hyperscaler along with a major storage OEM planned for calendar year '26.”
In November, TLC and QLC SSDs reportedly experienced strong price increases, with 1 TB TLC SSDs seeing sharp increases and the “most significant shortage due to persistent enterprise SSD demand.” 512 GB TLCs were estimated to see the most significant price hikes at ~65% MoM, while the QLC supply chain tightened and forced prices higher.
Additionally, TrendForce points out that these inventory and demand dynamics mean “supply shortages in 2026 are becoming increasingly apparent,” providing an additional lever for SSD prices to rise through next year and support more revenue growth as long as inventories and bit shipments do not hinder that.
Can the Memory Boom Last Through 2028?
There have been rising discussions regarding the strength of this current memory boom, and whether it can stretch through 2027 or even 2028, as reports from Korea and analysts from Morgan Stanley now estimate. The industry currently has the necessary ingredients for a sustained upcycle: strong demand, supply shortages combined with lean inventories, and strong pricing trends. A multi-year supercycle would likely require persistent supply shortages driving strong pricing power, stemming from elevated demand. such as strong HBM and LPDDR5X content growth with next-gen GPU racks, and strong inference-led tailwinds for SSD growth.
There are signs emerging that support such a view. Micron said in November that it is seeing “much more supply-demand tightness than we expected” in September and expects this tightness “to continue beyond 2026.” However, perhaps the most important comment from Micron came from Q1’s call this past week, with management saying that “in the medium term, we are only able to meet about 50% to 2/3 of our demand from several key customers.” SK Hynix also believes it will be “difficult to resolve the supply shortage by the first half of 2027.” More specifically on NAND, SanDisk says that demand “continued to outpace our supply, a dynamic we expect to persist through the end of calendar year '26 and beyond.”
Samsung and SK Hynix have both been rather straightforward about wanting to avoid oversupply, as this could cut the current cycle short and eat into profitability quickly. Samsung executives have said that they will “minimize the risk of oversupply through a capital expenditure strategy that balances customer demand and pricing," and instead of rapidly expanding production, they will focus on profitability.” SK Hynix is on a similar page, though reports have suggested it could boost 1c DRAM production by ~8X by 2026, from 20K units per month to 160K, in order to meet rising SOCAMM and GDDR7 demand.
The profitability point ties into capacity allocations and exhibits why supply remains tight. For example, HBM3e and DDR5 share production capacity, and through the first part of 2025, HBM3e “commanded a price premium more than four times that of DDR5.” However, with the recent surge in DDR5, profitability is now on track to surpass HBM3e by Q1, meaning suppliers may shift HBM3e capacity to DDR5 to boost profits. Samsung is already planning this shift from HBM3e to DDR5, with the expectation that it will shift ~80K wafers per month, while Micron is shelving its consumer DRAM and SSD unit, Crucial, to focus on HBM, DDR5 and enterprise SSDs.
Competitive risks aside, evidence of the size of this boom will be visible within revenue growth trajectories and margins. But perhaps the most important question for this cycle is, can the combination of tight supply, low inventories, sharply rising prices and strong (and rising) demand drive margins and earnings power to surpass 2018 levels in a sustainable way?
Currently, Micron’s revenue estimates and revisions give two primary takeaways into the duration and size of the cycle – analysts are more bullish about the boom lasting into 2028, though they are essentially completely divided on the overall strength of it, with revisions showing a massive range between low and high end forecasts.
Above shows revenue estimates heading into Micron’s fiscal Q1 report on December 17, with fiscal 2027 and fiscal 2028 both seeing estimates revised 41-43% higher since July. FY27 estimates had moved from $48 billion to $68 billion, while FY28 moved from $51 billion to $72 billion. A majority of the upward revisions have come since September, aligning with surging DRAM prices.
However, Micron gave a blowout Q2 guide, forecasting revenue of $18.7 billion at midpoint, more than 31% above consensus for $14.23 billion and representing growth of 37.1% QoQ and 132.2% YoY. This has pushed estimates even higher – FY26 and FY27 already see revisions ~$16 billion higher to $74.1 billion (+98% YoY), and $84.3 billion (+15%), while FY28 rose $11 billion and points to flat growth.
Analysts remain essentially completed divided on the potential strength of the cycle, with the gap between the low and high end of revenue estimates doubling from fiscal 2026 to fiscal 2027 and 2028.
For example, estimates for fiscal 2026 range from $53 billion on the low end to $82 billion on the high end, or a $29 billion range. For fiscal 2027, the low end falls to $46 billion, potentially on pricing peaking much sooner than expected, while the high end rises to $106 billion, a $59 billion range. Fiscal 2028 also sees a $61 billion range between the high and low end of $53 billion to $114.5 billion.
Source: Seeking Alpha
More impressively, Micron is showing that gross and operating margins have already surpassed the 2018 peaks, and commentary for expansion through the year suggests some potential upside to already strong earnings estimates.
For example, Micron’s TTM gross and operating margins, below, have rapidly recovered from 2023’s trough and already pushed past prior cyclical peaks (2010/2015), at 45.6% and 33% respectively as of fiscal Q1 (ending Aug). On a quarterly view, Micron’s FQ1 margins were 56% and 45% respectively, up 11.3 and 12.7 points QoQ. For comparison, SK Hynix reported operating margin at nearly 47% in Q3, up more than five points QoQ.
Compare this to the 2018 cycle, where DRAM prices tripled over the course of six to eight quarters. Micron’s gross and operating margins peaked at 60% and 50% respectively, and Q2 was guided to far surpass that at 67% and 58.7%, respectively. Again for comparison, SK Hynix’s operating margin peaked at 57% on a quarterly basis in Q3 2018, more than ten points higher than current margins.
Potential earnings power is where this boom gets interesting, especially for Micron, given the wide range for revenue estimates and the rapid ascent in margins to above >65%/>55%. Considering Micron’s management explained that they “would expect gross margins to expand beyond fiscal Q2” though at a more gradual pace than the last few quarters, it is reasonable to assume upside towards 70-72% and potentially 61-63% on operating margin, assuming similar fall-through. Supporting this would be evidence of strong AI-driven product demand in HBM and LPDDR5X (non-existent factors in the prior 2018 cycle) and strong DRAM pricing.
Assuming Micron ramps into this margin profile of ~70%/61% by year-end and maintains that through fiscal 2027 (Aug ’27) on tight supply dynamics and demand growth, rough back-of napkin math would place FY27 GAAP EPS at $40.35, or ~7.6% above consensus for $37.50 (although it should be noted that this was $20.77 prior to earnings, or an ~80.5% raise now).
If FY27 revenue moves to the upper end of the estimated range, or ~$105.8 billion, driven by factors such as strong HBM demand from next-gen platforms and strong LPDDR5X content growth, earnings power could be even stronger. Assuming the same peak margin profile of 70/61/54%, FY27 GAAP EPS could reach $50, or ~33% higher than consensus, though such a scenario could be challenging to execute.
However, it would be remiss to cover memory without discussing the cyclicality of the industry and risks to the ‘supercycle’ narrative. Some of the main factors that could end this cycle include potential oversupply from capacity additions, or price reverting lower after its current L-shaped trajectory.
While 16Gb DDR4 and DDR5 prices have seen an “unprecedented spot price rally” to record levels, time and time again DRAM prices have always reverted lower, although cycle timing can differ. The swiftness of the current price rally has already outpaced 2018’s rise, though the duration of the price rally has not nearly been long enough to see when or where it could peak. The next-gen DDR6 is not expected to reach the mass market until 2027, suggesting there is ample runway for DDR5 pricing to remain strong through 2026.
A more hidden risk to the thesis emerges from consumer electronics. Although Micron has exited its consumer memory business and the focus for the trio of Micron, SK Hynix and Samsung remains squarely on AI, consumer electronics (smartphones and PCs) are still strong drivers of DRAM and NAND demand. For example, some analysts have placed consumer electronics at ~37% of DRAM and ~56% of NAND demand.
The surging DRAM prices are placing upwards pressure on bill-of-materials content for PCs and smartphones, with Lenovo, Dell, HP, Asus and others already hiking PC prices as a result, estimated at around 15-20%. These dynamics could lead to inventory buildup in consumer electronics markets, or potentially some degree of demand erosion, both major headwinds for pricing strength moving through 2026 and 2027.
While inventory rebuild and oversupply have previously ended past booms, manufacturers are aiming to preserve strong profitability and avoid flooding the market to keep this cycle intact. However, there can be no assurance that these fears will remain on the back burner come 2027.
Conclusion
While this may be a lot to unpack, the primary takeaway here is that the memory market is seeing strong, structural tailwinds from rising HBM and LPDDR5X content in GPUs and SSD use in AI applications. Some of the primary companies located at the heart of this trend include Micron, SK Hynix and Samsung as the primary HBM manufacturers; for enterprise SSDs, the market leaders include Micron, Samsung, SK, Kioxia and SanDisk.
To help narrow down on this trend, we plan to dive deeper into one of a leading Memory stock to our Discovery tier members the first week of January.
Subscribe to Discovery and get the Top 10 Emerging Tech Watchlist delivered monthly. Our incoming Top 10 list will be published January 2nd with many new names including a lesser-known memory stock. Current Pro and Advanced Members: To subscribe to Discovery with 30% off, click here to email us or email premium@io-fund.com and mention code DISCOVERY30
Please note: The I/O Fund conducts research and draws conclusions for the Fund’s positions. We then share that information with our readers. This is not a guarantee of a stock’s performance. Please consult your personal financial advisor before buying any stock in the companies mentioned in this analysis.
Recommended Reading: