a947dd97-abc6-4aea-8ad9-4fcf40b83950_AMD-Xilinx-Acquisition-Analysis.pdf

AMD-Xilinx Acquisition: Analysis

You can access my original analysis on Xilinx here.

 It would be impossible to look at the AMD-Xilinx acquisition without doing an in-depth breakdown of FPGAs. The chips are powerful yet are challenging to program, and therefore, adoption has been slower than originally forecasted around 2016-2018.

 Around the time that I began writing on Nvidia, I was also covering Xilinx. At the time, the company was very promising as Microsoft was adopting FPGAs and the chips were slated to be a front-runner for 5G networks. This began to change, however, when Nokia announced they were moving away from Intel-Altera’s FPGAs after the poor results discussed in Q3 2019. 

Below, I compare GPUs with FPGAs and ASICs to help break down the potential strengths for the AMD-Xilinx acquisition, especially why a predominantly CPU-company would acquire a FPGA-company. We discuss the headwinds for FPGAs and Xilinx and how AMD could potentially alleviate these. 

For our purposes, we will call these chips data accelerator chips or AI chips. As you know, GPUs, ASICs/SoCs and FPGAs have many other uses (gaming, PCs, smartphones, electronics), but as tech growth investors, we are mainly interested in modern data centers and cloud IaaS infrastructure that can handle the increase of networking bandwidth and optimization of AI workloads. By accelerating the computing platform, these chips can power machine learning, deep learning and high-performance computing workloads. The leading chips will have quite the addressable market to capture and we want to be there when this happens.

The data center accelerator market was forecast to grow 49.47% CAGR between 2018-2023 from $1.4 billion in 2017 to $21.2 billion in 2023. At the time of the forecast, FPGAs were forecast to be the leading chip in terms of growth but this has not materialized (we cover this below). According to a more recent report in May of 2020, the global accelerator market will reach $38.9 billion with GPUs growing at a compounded rate of 47.1% 

The growing need for cloud resources is driving a healthy market for hyperscale data centers with an expected increase of 60% between 2016 and 2021. We are also seeing substantial investments in next-generation data centers due to the pandemic, such as Alibaba’s announcement to invest RMB 200 billion in core technologies and future-oriented data centers. 

When it comes to processors, the question is which chip will answer the demand. This is a question that has not been fully answered yet although GPUs are almost universal for general AI due to the ease of development for software engineers, ASICs are gaining popularity with Google and others who seek application-specific  advantages, and FPGAs are continually forecast to lead the growth but sees roadblocks in the learning curve for hardware configuration.

The competition between FPGAs and ASICs could also be alleviated by combining an Arm-based processor with an FPGA. The Zynq-7000 SoC allows for dedicated hardware blocs to split-up non-critical tasks from critical tasks. I imagine AMD fully comprehends the strengths and weaknesses of FPGAs and is set to solve the developer adoption uptake should the acquisition go through.

Overview of GPUs, FPGAs and ASICs:

General Definitions:

GPU: graphics processing unit with a highly parallel structure compared to CPUs. When training deep learning neural networks, GPUs are up to 250 times faster than CPUs. When compared to FPGAs and ASICs, GPUs continue to lead due to the learning curve for software developers and not requiring changes to existing code. Notably, GPUs originated as graphics cards used in gaming but now lead in general AI processors. Nvidia is the major GPU player.

FPGA: field-programmable gate arrays that can be programmed electronically “in the field” post-manufacturing after the chip leaves the foundry. The chip is made up of configurable logic blocks and programmable interconnects that allow for the chips to be reprogrammed. FPGAs are preferred for prototyping or for instances where the design may evolve. Designing with FPGAs are low cost but can become expensive over time. Intel and Xilinx are the major FPGA players.

A few points to note:

•       FPGAs increase real-time inference compared to CPUs and reduce latency compared to GPUs. 

•       FPGAs chips are also cheaper and also faster to bring to market than ASICs (although this is not an advantage for high production volumes — more below including a visualization of this). 

•       FPGAs are unique from ASICs and GPUs due to being customizable post-manufacturing. The “fieldprogrammable” piece is unique to FPGAs.

•       There are new products being released all of the time that aim to get an advantage between ASICs and FPGAs, but for the most part, these two are similar in latency and somewhat similar in power efficiency except ASICs technically lead here due to being application-specific. The design needs will often determine the decision between ASICs and FPGAs and the production volume. Notably, FPGAs will often be used for prototyping before switching to ASICs.

•       The drawback to FPGAs is the complexity in programming as software engineers are not as familiar with hardware-specific languages. 

ASIC: application-specific integrated circuit customized for a specific application. If an ASIC has more than one processor core and/or combines various computer components, then it’s considered an SoC. You’ll hear these words used interchangeably (ASIC/SoC) on earnings calls.

ASICs are preferred for large production volumes as the cost for design can be in the millions of dollars but then averages out over time.

•       Google is the perfect example of a company that uses ASICs as the company has many servers dedicated to solving specific problems.  

•       These chips, including Google’s TPU, can be designed for maximum efficiency by shifting the optimization and resource assignments to the CPU with the TPU/ASIC acting as a coprocessor for vertical instructions. 

•       Some companies may find ASICs to be too rigid and fixed. As of recently, Microsoft for example has preferred FPGAs as there is more flexibility in the design. 

Expanding on these Definitions:

For most design purposes, FPGAs (Xilinx) are considered superior to GPUs (Nvidia) when it comes to power efficiency. They offer a higher amount of on-chip cache memory to help reduce the bottlenecks from external memory, and are flexible enough to be reconfigured for various data types, such as binary, ternary, and custom data types, whereas GPUs must be modified at the vendor level. With that said, Nvidia will likely leverage Mellanox to speed up GPUs and close the gap on latency performance with FPGAs and ASICs.  

GPUs are programmed at the foundry and are restricted by Single Instruction Multiple Thread (SIMT), which provides an advantage over CPUs, but can also result in lower performance efficiency when enough parallels are not found for the workload. 

Despite FPGAs resulting in faster high-performance computing, they are harder to program due to hardware circuit configurations compared to GPUs for machine learning, which require less engineering resources due to being programmed through software. FPGAs are generally run with high-level languages such as VHDL or Verilog. GPUs are also more cost efficient. 

Source: GPU vs FPGA Performance Comparison

ASICs rival FPGAs on efficiency and power (and often beats FPGAs in these areas for specific workloads) and this is one reason why we’ve seen ASICs become more popular in recent years. The difference between these two is reconfigurability. This is a major advantage for end applications and workloads as the chip can be programmed “in the field” after it’s left the foundry. As discussed, the reconfigurability is what the acronym FPGA stands for – Field-programmable gate array. You can program the chip to be a microprocessor, graphics card or encryption unit.

ASICS are Application-specific Integrated Circuits and are designed to be application-specific for one purpose only. The circuitry cannot be changed because it is made up of permanent circuitry. You use ASICs every day in your smartphone, laptop and television. 

ASICs have high “non-recurring engineering” costs (NRE) and are more expensive at the onset.

However, FPGAs come at an increased cost after a certain time period and have limited analog functionality. Therefore, FPGAs actually cost more overall because the cost of ASICs becomes lower with higher production. 

FPGAs have limited analog functionality, such as Bluetooth and WiFi. This is why ASICs are the chosen chip for electronic devices. “Low power” is also a major advantage to ASICs which makes the chips ideal for specific battery-operated devices.

Here is a picture I provided in Marvell’s PDF. What this picture is showing is that it costs millions to begin with ASICs and less than $5000 to begin with FPGAs. However, over time, the cost of FPGAs exceeds that of ASICs.

FPGAs are used more for prototyping due to the reconfigurability and due to ASICs requiring more during the design process. ASICs take months longer to implement due to the manufacturing cycle, and as mentioned above, cost quite a bit at the onset. The R&D cycle for ASICs can become problematic when companies are competing neck-to-neck for market share. 

FPGAs in Real Use Cases

We want to be clear that we are ultimately bullish on the AMD-Xilinx acquisition as we believe AMD has what it takes to bridge FPGAs. In the use cases below, you will see there are some mixed results with FPGAs competitively which is likely leading to Xilinx looking at an offer. 

The Nvidia-Mellanox-Arm combination is a looming threat, as well, and if AMD can make FPGAs more accessible, then this will provide AMD with critical market share in data center acceleration/AI chips without having to compete with Nvidia head-on with GPUs.

Xilinx’s Segments

ABC: Automotive, Broadcast and Consumer

AIT: Aerospace and Defense, Industrial, Test and Measurement

DCG: Data Center Group

ISM: Industrial, Scientific & Medical

TME: Test, Measurement & Emulation

WWG: Wired and Wireless Group

Aerospace/Defense and Automotive:

Xilinx leads in aerospace/defense and automotive. These are industries where FPGAs have a clear advantage. 

In May, Xilinx announced the first 20-nanometer (nm) space-grade FPGA to deliver machine-learning for space applications. This allows satellites to update in real-time, deliver video-on-demand, and perform compute “onthe-fly” to process complex algorithms.

Although autonomous driving is very new and the market is wide open, FPGAs beat GPUs in many regards for this application. This is likely part of Intel’s motivation in buying Altera. This space is constantly evolving but here is a recent quote from a product manager in the field, “Autonomous vehicles rely a great deal on machine learning, and every new vehicle in every new situation may contribute to the shared knowledge base,” said Tobias Welp, product manager at OneSpin Solutions. 

FPGAs offer flexibility for many applications because both the hardware and the software can be reprogrammed. Reprogramming FPGAs when knowledge or algorithms are enhanced has the potential to keep autonomous driving in a state of continuous improvement.”

But there are tradeoffs. Verification in this case becomes a continuous process.“Every time the design changes, the full verification suite (static, formal, and simulation) must be run,” Welp said. “Formal equivalence checking also must be run to ensure that the FPGAs have no implementation errors, security vulnerabilities, or lurking hardware Trojans. Finally, the reprogrammed FPGAs must be extensively validated on test vehicles before updates are sent to the field.”

In regards to ASICs and how AVs are in constant flux, here is what Welp stated:

“When we started in this space and we were talking to automotive customers a year ago, everybody was going straight to Level 4 and Level 5 autonomous,” said Geoff Tate, CEO of Flex Logix. “They were all going to do their own custom chips. They were all looking to license IP for inference acceleration. That’s changed dramatically. I don’t know of anybody who’s looking to do an ASIC in the automotive space right now. Everybody that was telling us they’re going do their own chips has changed to buying off-the-shelf chips, and almost all the major car companies are focused more on driver assist.”

Therefore, we see that FPGAs have a serious shot here at being the chosen chip for AV development. 

Wired and Wireless Group:

Xilinx saw a significant slowdown in the wired and wireless group in the previous quarter due to supplying Huawei but some of this growth has returned. The Nokia-Intel FPGA flop in November 2019 has hurt the prospects for using FPGAs in 5G with Nokia turning more towards ASICs/Marvell. 

Originally, Nokia stated that FPGAs seemed like the best choice because 5G standards were not developed yet and the flexibility was key. However, as we’ve illustrated in this analysis and covered in the Marvell PDF, ASICs cost less over time and this is becoming a priority for Nokia to protect their bottom line on the already-expensive 5G infrastructure overhaul. In an earnings call, Nokia’s CEO lamented that FPGAs were more costly than anticipated.

The CEO discusses the situation in the Q3 2019 transcript and also the Q4 2019 transcript. Here are some excerpts:

So, what’s happening right now is when he moved to 5G, we chose FPGA-based products. They give you flexibility, they give you time to market advantage, but then they’re expensive. And so, what we’re doing is, we’re moving to equity SoC-based products, which we’ll progressively start shipping during 2020. -Q3 2019 earnings call

Like I said earlier, I mean, the System on Chip strategy has been put into motion already a while ago, diversified our supplier base. We are increasing the investments purely because we want to increase even more the SoC penetration in our products and continue that. And of course, we know how to do System on Chip. Yes, we started with FPGA with 5G because it’s gave us that time to market catch-up advantage, but we do that in much of our portfolio with FP4 and PSE-3. So, we’re just replicating that in mobile. –Q3 2019 earnings call

And Tal, on the question regarding to System on Chip, so we are transitioning from FPGA to System on Chip and this is the metric that will give you an update and this is that we got to 10% of the 5G product by ReefShark System on Chip portfolio. We started ramping up volumes and that will get to 35% by the end of this year or greater than 35% and then 70% by the end of ‘21 and then this whole thing will be complete about 100% in 2022.  -Q4 2019 earnings call, when an analyst asked for an update in moving from FPGA to SoC.

Despite Nokia’s decision, FPGA-proponents for 5G will argue that these chips are ideal for network infrastructure to prevent vendor lock-in and for futureproofing the network due to the ability to reprogram. In this way, FPGAs could reduce long-term operating expenses and reduce total cost of ownership. 

You can access a full list of Xilinx’s segments here and how the company serves each of these markets, including Industrial, Medical and Video Processing. 

High-Performance Supercomputing

FPGAs and high-performance computing (HPC) is an important part of data center acceleration that can benefit from easier programming options. This is because FPGAs are known to be pliable when involving interconnects and this is valuable for supercomputers. 

This will not replace GPUs rather it will serve applications with heavy computations. FPGAs can optimize purposebuilt architecture and there is a high probability we will see the supercomputers of the future powered by a combination of CPUs/GPUs and FPGAs. As of now, Nvidia is the undisputed leader in the data center. In fact, as of May 2019, Nvidia was employed in 97.4% of cloud IaaS compute instance types with dedicated accelerators with combined Xilinx and Intel at 1.6%. 

Liftr Insights shows a slightly better picture for FPGAs at about 5% for Xilinx and a little under 5% for Intel across Alibaba, AWS and Azure in March of 2020. The analysis firm puts Nvidia at 86% in this study.  

Source: EETimes.com

In 2015, Intel acquired Altera in an all-cash transaction worth $16.7 billion. Altera was second to Xilinx as a leading provider of FPGAs. This acquisition occurred during the years that FPGAs were favored for data center growth over its counterparts yet Intel has not been able to penetrate data centers with this acquisition as originally estimated. This could be for two reasons: (1) FPGAs are more advanced and will rise in popularity after general AI is exhausted and more complexity is required by the market (2) ASICs are superior to FPGAs and are meeting the market demand with customizable that was once assumed would be met by field-programmable.

In 2018, Microsoft announced it would be phasing out Intel-Altera FPGAs for over half its servers in favor of Xilinx’s processors. This was confirmed again in October of 2019 by Microsoft at a Xilinx conference although no official update for two years now. At the time, I guessed this move by Microsoft was due to AI engineers preferring Xilinx over Intel, which I still believe to be the case when FPGAs are being considered. 

It should be noted that AMD is already solid in the supercomputer category with Epyc CPUs powering many of the supercomputers in the top 500 list. Here’s a great write-up from Moor Insights on AMD’s partnership with HP’s supercomputer manufacturer Cray. The partnership is expected to launch the second Exascale system in the United States costing over $600 million. The Frontier Supercomputer is expected to put AMD on the map for AI accelerators and as a competitor to Nvidia.

Constantly Evolving:

Xilinx’s SDAccel IDE has attempted to provide software developers the same experience no matter the cloud provider (AWS, Alibaba, etc). The goal was to copy Nvidia’s CUDA platform to enable a larger ecosystem. The tool platform is called “Vitis” and is designed to provide accessibility for hardware developers and software developers. The first release of SDAccel supported deep learning frameworks, such as Caffe, MXNet and TensorFlow through Python APIs. 

AMD backed Xilinx around this time for the Alveo model launch for machine learning, which was the first supported environment on Xilinx’s SDAccel IDE. Alveo was dubbed “the world’s fastest data center and accelerator cards” to increase real-time inference throughput by 20X compared to CPUs and 3X compared to GPUs. AMD offers Radeon Instinct accelerator cards built on Vega 7nm GPUs.

Xilinx also launched the “Versal” advanced computing acceleration platform. This is a fully softwareprogrammable heterogeneous compute platform that improves performance 20X over current FPGAs and 100X over CPUs (per Xilinx’s white paper). The SoC-like chips combine CPU cores, programmable logic and ASIC elements. This was around the time that Xilinx stopped referring to itself as a FPGA company and instead as a platform company with a focus on “whole application acceleration.”   

The Versal series includes AI engines in the device series, such as Versal AI Edge, Versal AI Core and Versal AI RF. Xilinx aims to not only accelerate the AI portion of the task but to combine AI engines with DSP engines and also adaptive engines to accelerate the entire task, such as beamforming for 5G radar wireless communications or for smart controllers for storage systems in data centers. 

Financials:

Advanced Micro Devices reported Q2 results on July 28th, beating comfortably on both the top and bottom lines.  Revenue came in at $1.93B (+26% YoY), representing a beat of $70M above consensus estimates.  Management attributed the revenue growth primarily to higher Computing and Graphics segment revenue.  

Non-GAAP EPS grew 333% YoY to $0.18 per share in the quarter.  Gross margin increased 3 percentage points YoY to 44%, primarily driven by Ryzen™ and EPYC™ processor sales.  For the 3rd quarter and FY, management is calling for an acceleration of revenue growth to 42% YoY and 32% for FY 2020. 

Xilinx reported Fiscal Q1 results on July 30th, reporting a slight miss on the top line and a slight beat on the bottom line.  Revenue decelerated 14% YoY to just under $727M, missing consensus estimates by about $1M.  Non-GAAP EPS decelerated 33% YoY to $0.65 per share, beating the consensus by half a cent.  The company made no adjustments to its outlook and expects to record $755M in revenue in its next quarter.

At a listed acquisition price of $30B, Xilinx would be valued at 10x sales.  Xilinx has 244.3M shares outstanding and the company is projected to deliver $3.54 in EPS in FY 2022, meaning they are on pace for $864M in net income in 2022.  

At an acquisition price of $30B, AMD would need to issue 361M shares in an all-stock deal for Xilinx.  In 2022, AMD is projected to deliver $2.20 in EPS.  With $1.17B shares outstanding, the company is on pace for approximately $2.6B in net income for FY 2022.  

In order for the deal to be accretive for AMD, the Xilinx business has to generate approximately $800M in 2022 annual net income. The Xilinx standalone business is projected to generate $864M in annual profits in 2022.  

If the acquisition price exceeds $30B, an all-stock deal may become dilutive.  At an acquisition price of $35B, AMD would need to issue 422M shares to acquire Xilinx. This would require the Xilinx business to generate $1B in 2022 net income for the deal to be accretive.  

Conclusion: 

On a technical level, workloads like machine learning, AI and 5G can benefit from a chip that is field-programmable and bridges the gap with customized chips that take too long to bring-to-market. Xilinx’s FPGAs allow algorithms to be adjusted for critical technologies and R&D processes. 

This space is constantly evolving. FPGAs also have SOC-chips that Xilinx calls “all programmable SOCs.” Hard-silicon processor cores are being combined with FPGAs to compete with ASICs. In this case, an ARM Cortex A9 and Xilinx Zynq become dedicated hardware blocs to split up non-critical tasks from tasks requiring high-speed acceleration. 

The question is can AMD do this for Xilinx versus Nvidia in key markets:

When it comes to efficiency, AMD is an unstoppable powerhouse. There are leaks that the 7nm Milan release will achieve a higher clock rate with performance increases of 10-20% between generations. This is virtually unheard of.

Lisa Su brought AMD from a $3 billion market cap to a $100 billion market cap in 5 years. As of now, we see Xilinx spread across too many segments and lacking focus. If AMD can popularize a platform for Xilinx/FPGAs that competes with CUDA and chooses the segments where FPGAs have the most promise, then we could see FPGAs finally live up to their true potential. 

AMD under Lisa Su as CEO has risen 2000% over the past 5 years

I believe there will be quite a few negative opinions about AMD’s move with Xilinx. Analysts will say Nvidia has the undisputed throne, there is no overlap with AMD-Xilinx, that the acquisition is too expensive and dilutes shareholder value and that AMD does not have enough successful acquisitions under its belt to gamble on this combination. 

Others may not see why AMD would acquire Xilinx, but I’ve been waiting for something to happen with FPGAs and this very well could be it. We had discussed AMD innovating past Intel prior to this happening in July. Our premium members were pretty happy about that call. On a similar note, I’ve been tracking Xilinx closely, waiting for a breakthrough of some sort. 

Of course, I am a mega Nvidia bull and this will not change. This will not be a winner-takes-all market, rather a market that compounds quickly for the top handful of companies. There are a few CEOs I won’t be against and Lisa Su is one of them. 

Grab some popcorn because it’s going to get pretty exciting between 2022-2025 as Su and Huang dual it out. My prediction is they will both take enough market share for my premium subs to remember these calls as some of my very best.